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Chapter 2: Getting Started
SOPC Builder Design Flow
SOPC Builder generates the SOPC Builder system files. You must create a top-level
design that instantiates the SOPC Builder system, PLL(s) and a DLL, before you
In addition to the SOPC Builder system files, SOPC Builder generates an example
design, < variation name > _debug_design.v or .vhd . The example design contains the
DDR or DDR2 SDRAM Controller, PLL, and the example driver; it has no SOPC
Builder components (refer to Figure 1–1 on page 1–3 ).
You can use the example design to test boards and simulate, to understand the DDR
or DDR2 SDRAM interface.
Create Your Top-Level Design
Use the example design, < variation name > _debug_design.v or .vhd , as a guide to
connect and instantiate the PLL, the optional fed-back PLL, and DLL, to your SOPC
Builder system. You must remove the example driver and the controller, and replace
them with the SOPC Builder-generated system (refer to Figure 2–1 ).
1
f
To ensure that the wizard-generated constraints are correctly applied, either allow the
constraints script to automatically detect your hierarchy, or ensure that the hierarchy
and pin names on the Hierarchy tab match those names in your HDL.
For more example designs, refer to the Cyclone II reference designs in the Nios ? II
Development Kit.
Figure 2–1. SOPC Builder System with the DDR SDRAM Controller
Editted Example Top-Level Design
SOPC Builder System
Avalon
UART, etc.
PLL
DLL (1)
Other
SOPC Builder
Components
Switch
Fabric
DDR SDRAM
Controller
DDR SDRAM
Interface
DDR SDRAM
Simulate the SOPC Builder Design
To simulate the SOPC Builder design, either use the Nios II simulation flow or create
your own testbench instantiating the top-level design and a memory model.
f
For more information on the Nios II simulation flow, refer to volume 4 of the Quartus
II Handbook .
Compile the SOPC Builder Design
You can now edit the PLL(s) and use the Quartus II software to compile the example
design and perform post-compilation timing analysis.
? March 2009 Altera Corporation
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